tri-state input in FSM

Hardware input state can't be high z, it's either low or high, or possibly an intermediate voltage of unclear level. z input state can possibly occur in simulation.

I don't know however, what you mean with a "don't care state" of the FSM. I guess, you are rather talking about an illegal state which can be brought up by timing violations, if asynchronous input signals to a state machine aren't properly registered.

Besides registering of input signals, forcing safe state machine encoding should be able to avoid the problem. Refer to the Quartus Software Handbook.

Can you please clarify, if you talk about simulation or hardware behaviour?