Tri-state bus data bus delayed

Dear Sheng,

Thank you for your reply.

I looked at those posts and the only thing that I saw that seemed relevant to my design was "when CASE or IF statements do not cover all possible input conditions...". In my SM for both the read and write cycles I use a CASE statement and I added the code :-

when others =>
usbD <= (others => '0'); -- DEBUG USB429
end case;

However this didn't help, the clocked register shown in USB429 - usbD birectional output implementation - Technology Map Viewer 2.jpg above still exits and on the scope the output data is still delayed by 1 clock ?

Any other ideas ?

Best regards

shmuel