transfer Analog to Digital (count time between two pulses)

Depends on the intended time resolution. Timing measurements down to about 1 ns can be implemented with pure digital methods, e.g. using SERDES blocks, possibly with mutiple phase shifted clocks.

For high resolution timing mesurements, e.g. 10 ps or better resolution, there's no straightforward solution with FPGAs. You find TDC (time-to-digital converters) utilizing logic gate delay described in literature, also with Altera FPGA. See previous threads in the Altera forum. But these designs are fighting various problems like unpredictable and hard to control routing delay.

Referring to state-of-the-art external TDC circuits might be the easier approach.