Transceivers on a GX FPGA - to use or not to use?

Hi Mike,

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I am designing a custom board using a Stratix IV GX FPGA for the first time (EP4SGX70HF35). I'm interfacing three 16-bit ADCs to the FPGA and was considering using transceivers to receive the LVDS data. Do I need to implement a special megafunction (ALTGX) to use the transceiver pins or can they be treated as regular I/O pins?

The bandwidth of the ADCs is not very high (less than 1 Gbps). Is there any benefit to using the transceivers?

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You cannot (easily) interface an arbitrary LVDS signal to a transceiver channel. Transceiver channels 'like' to receive modulated signals such that their clock-and-data recovery PLLs (CDRs) can lock-to-data and then recover the data.

For applications under 1Gbps you're better off to stick with the LVDS receivers.

Here's a 1GHz digitizer design with test results for LVDS at 1Gbps and 500Mbps.

http://www.ovro.caltech.edu/~dwh/carma_board/

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf

Cheers,

Dave

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Hi Mike,

You cannot (easily) interface an arbitrary LVDS signal to a transceiver channel. Transceiver channels 'like' to receive modulated signals such that their clock-and-data recovery PLLs (CDRs) can lock-to-data and then recover the data.

For applications under 1Gbps you're better off to stick with the LVDS receivers.

Here's a 1GHz digitizer design with test results for LVDS at 1Gbps and 500Mbps.

http://www.ovro.caltech.edu/~dwh/carma_board/

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf

Cheers,

Dave

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Unless you're using an ADC that's JEDEC JESD204 or 204A compliant, you're better off staying with LVDS. JESD204/A embeds the clock in with the data which is what transceivers like (per dwh's comment). JESD204/A ADCs make board routing easier, but there's still a limited selection available on the market.

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Dave, fpgajeg,

Thanks for the responses. This is my first time utilizing a GX part so I was curious to see if there was any benefit to using the transceivers for my application. It seems like there is not and they would just add complication. I've been interfacing ADCs with FPGAs for quite some time so I will go ahead and use the normal LVDS receiver pins. The ADC I'm using does not comply with the JEDEC or JESD204 standard.

That's an impressive paper Dave. Glad that you're helping out in this forum.

-Mike