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Altera_Forum
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14 years ago

Transceiver Pseudo-CML equivalent circuit?

I'm currently testing with the Stratix IV GX development kit and would like to know if anyone has details on the equivalent circuit for the transmitter.

A CML driver typically consists of a differential pair terminated in 50-ohms to a termination voltage, a current sink, and current steering logic, as shown on p9 of this data sheet

http://www.analog.com/static/imported-files/data_sheets/adcmp572_573.pdf

(nothing special about this part, it just had a CML driver circuit diagram).

The CML transmitter outputs high and low voltages by steering current through one of the differential signals, i.e., in the data sheet above, one of the transistors is on, while the other is off.

The Stratix IV handbook has the circuit diagram for a DC coupled link between a Stratix IV GX transmitter and receiver on p1-45 of Volume 2 (p489 of the PDF).

http://www.altera.com/literature/hb/stratix-iv/stratix4_handbook.pdf

However, this diagram does not show how the transmitter buffer is implemented.

If I assume that the buffer sinks current according to the CML driver circuit in the Analog Devices data sheet above, then I can draw an equivalent circuit in LTSpice to calculate the DC currents and voltages (yeah, I can do the same with a piece of paper and a calculator too). For a transmit termination voltage of 0.65V and receiver termination voltage of 0.82V, the result is a logic high voltage of 735mV and a logic low of 435mV, assuming 50-ohm terminations and a transmitter current sink of 12mA (the transmitter Vod setting can be used to adjust this).

The problem is that I observe a logic high of 910mV and a logic low of 540mV. The fact that the observed logic high is greater than 735mV, means that the receiver termination resistor is actually sinking ~2mA (to develop ~100mV across it), meaning the driver is sourcing ~2mA current.

This is inconsistent with the CML driver circuit. However, perhaps that is the meaning of pseudo in pseudo-CML :)

Anyone have any insight into this?

Cheers,

Dave

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi Dajun,

    --- Quote Start ---

    But I really want to know the maxium sink/source current capability of transimit termination resistors, because I want to terminate the transimit signals using standard 1.5-V CML termination method at the receiver end (the receiver is a programmable delay chip), which will give about a maxium of 12mA sink current through the internal termination resister in ArriaII GX. I really would like to know whether this 12mA current will damage the output buffer of transimitter in FPGA?

    --- Quote End ---

    I don't know the answer to this. How about you submit a service request to Altera directly, and then post their response here? That would be very helpful.

    Cheers,

    Dave