Forum Discussion
CStoe2
New Contributor
New ContributorTransceiver in Cyclone V using less then 614 Mbps
Hi all, In a recent project I would like to use a camera with a clock of 290 MHz when using Double Data Rate. The throughput rate is therefore 580 Mbps per channel for a total of 10 channels. Now i...
CheepinC_altera
Regular Contributor
Regular ContributorHi,
As I understand it, you have some inquiries related to the CV transceiver data rate. Yes, you are right, the minimum supported data rate of the CV transceiver is 614Mbps. Your targeted 580Mbps is out of the minimum supported specs.
As an alternative, just wonder if you have had a chance to look into LVDS SERDES which should be able to support the specific data rate of yours as well as deserialization factor from 4 to 10.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
CStoe2New Contributor
New ContributorHi,
thanks for your answer.
The document "Cyclone V Device Interfaces and Integration Document" describes that "the In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively". As a result, the LVDS Reciever does not use the data path with the deserializer for my DDR data input. In my understanding, the design would then be routed just like mine, which uses the DDIO blocks.
I have to say that I drive the DDIO IP directly with the clock from the input pin and no intermediate PLL for the data clock. Can this possibly fix the timing issues? I initially tried to use the PLL, but I was overwhelmed by setting the constraints associated with the DDIO block.
Best regards,
Christian
