Honored ContributorMy goal is to show priorities of all interrupts.
So i picked up registers ICDIPRn The number of those are 8*(ICDICTR.ITLinesNumber+1) according to GIC_architecture_spec_v1_0.pdf (4.3.10) I am running Altera's SoC Dev Kit with GHRD and Altera's baremetal example. My calculations are 64 ICDIPR registers. Can someone confirm?
Honored ContributorYes, its logically, only in 32-bit words, you know that in ICDICTR have only 5 bits for coding ITLinesNumber, and need be encode 1024==2^10 values...
Altera expand ARM-core for GIC to 256 inputs, and last defined value in alt_interrupt_common.h (in "typedef enum ALT_INT_INTERRUPT_e") is 211, better for keep in mind will be 60 from your 64... :) In GIC 2.0 these registers is renamed for usability, however (8*( +1)) is remain. In alt_interrupt.c in alt_init_global_init() variable alt_int_count_int computes through "<<5" ! In DS-5 debugger is visible GIC registers ? I not found its neither in Core, CP15, Peripherals... I not see in "Registers" window propeprty "Refresh continuosly", for these registers or memory content may be very usable. I want try no enable HPS interrupts global to poll requests from buttons in GIC register contents. And not found one register or some, poll which may get info about "quiet" waiting interrupt. 4K address space not give so small info ! Or I is wrong ? Simply registers 300..37C "Active bit" show 1 if "interrupt is active or active and pending", one "common" register with pending indicating in GIC not visible... Before calling IRQ-handler is no indication of forthcoming event ?Honored ContributorSorry, yesterday I was wrong, now found register ICCHPIR in GIC-"CPU interface", what contain same important interrupt IRQ or 3FF if none.
If will not enable bit I in CSPR register (alt_int_cpu_enable() function), then interrupt not cause though works GIC and bit CP14_ISR.I is set to ARM-processor. And polling of register ICCHPIR point to same priorited query !
