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Altera_Forum
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10 years ago

tLTD value of Arria V FPGA

Hi, I'm using Arria V series FPGA. In the device datasheet, tLTR (time of the receiver CDR to lock to the ref clock) is specified as maximum of 10 us. But tLTD(time to start recovering valid da...
Altera_Forum's avatar
Altera_Forum
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10 years ago

It simply means you must wait at least 4us before trusting the data that comes from the CDR. I too feel the wording is poor. Perhaps more appropriate - 'tLTD is the time to wait for the receiver CDR to start recovering valid data...'.

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Does it mean CDR MUST not lock to data within 4 us?

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No. However, the data is only guaranteed to be correct 4us after 'rx_is_lockedtodata' signal goes high.

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How can I get the maximum value of tLTD?

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Assuming what I've already written is true, this is no longer relevant.

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Is the receiving data ALWAYS correct after tLTD?

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Subject to all conditions remaining within the parameters defined in the datasheet - yes - that should hold true.

Cheers,

Alex