Timing Problem(Clock Edge)

Also I would look at the structure of your process. You have to be very strict with your coding style for synthesis:

process (clk, reset_n, async_load)
begin
if reset_n = '0' then
    -- ansynchonous clear assignments
elsif async_load = '1' then
    -- asynchronous load assignments
elsif rising_edge(clk) then
    -- put your register assignments (i.e. your state machine) in here
end if;
end process

Of course you don't have to have the asynchronous reset or load in there:

process (clk)
begin
if rising_edge(clk) then
    -- put your register assignments (i.e. your state machine) in here
end if;
end process

Don't be tempted to add anything else into the rising_edge(clk) line as this will give you a gated clock.

Altera have some guidelines on coding for synthesis (which are pretty much the same as other FPGA manufacturers):

http://www.altera.com/literature/hb/...din g%20style (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=coding%20style)

By the way the "clk'event and clk = '1'" notation that you've used is fine and basically the same as "rising_edge(clk)" - the only real difference is that the latter works with transitions like 'L' to 'H' in simulation - for synthesis it won't make a difference.

I would start by tweaking your code to comply with this sort of standard and I'm sure you will get rid of the errors, a whole load more warnings that you haven't noticed yet and a whole load of nasties still waiting in the wings.

Probably something like this:

process (CLK,RST)
begin
if RST = '1' then
    state <= s0;
    Digit1 <= (others=>'0');
    Digit10 <= (others=>'0');
elsif CLK'event and CLK = '1' then
    if pedestrian = '1' then
        state <= s4;
    else
        case state is
                when s0 =>
             -- etc etc
    end if;
end if;
end process

Your pedestrian signal is now effectively a synchronous reset but note that the reset and clk conditions are as above.

Hope this helps - the coding style document is really worth a read.