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Altera_Forum
Honored Contributor
Honored ContributorTiming Problem(Clock Edge)
Dear all, I'm new to VHDL and need all u guys out there, I'm currently designning a VHDL code for traffic light (two processes) coding style and i bump to this error regarding clock timi...
Altera_ForumHonored Contributor
Honored ContributorYou are missing some elses in the main process... You should start with replacing the two ifs (on RST and CLK'event) with elsifs and see what happens
