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Honored ContributorTiming Problem(Clock Edge)
Dear all, I'm new to VHDL and need all u guys out there, I'm currently designning a VHDL code for traffic light (two processes) coding style and i bump to this error regarding clock timi...
Altera_ForumHonored Contributor
Honored Contributorhere is de code:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity traffic is port ( CLK : in std_logic; RST : in std_logic; car : in std_logic; pedestrian : in std_logic; Digit1_o : out unsigned (3 downto 0); Digit10_o : out unsigned (3 downto 0); lights : out std_logic_vector (6 downto 0) ); end traffic; architecture traffic_arch of traffic is type state_type is (s0,s1,s2,s3,s4,s5,s6,s7); signal state : state_type; signal Digit1 : unsigned (3 downto 0); signal Digit10 : unsigned (3 downto 0); begin main:process(CLK,RST,car,pedestrian) begin if pedestrian = '1' then state <= s4; if RST = '1' then state <= s0; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); if CLK'event and CLK = '1' then case state is when s0 => if Digit1 < 9 then state <= s0; Digit1 <= Digit1 + 1; if Digit10 < 5 then state <= s0; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s1; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); end if; end if; when s1 => if (car = '1') then state <= s2; else if Digit1 < 9 then state <= s1; Digit1 <= Digit1 + 1; if Digit10 < 2 then state <= s1; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s2; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); end if; end if; end if; when s2 => if Digit1 < 9 then state <= s2; Digit1 <= Digit1 + 1; if Digit10 < 0 then state <= s2; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s3; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); end if; end if; when s3 => if Digit1 < 2 then state <= s3; Digit1 <= Digit1 + 1; if Digit10 < 0 then state <= s3; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s4; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); end if; end if; when s4 => if Digit1 < 9 then state <= s4; Digit1 <= Digit1 + 1; if Digit10 < 2 then state <= s4; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s5; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); end if; end if; when s5 => if (car = '1') then if Digit1 < 9 then state <= s5; Digit1 <= Digit1 + 1; if Digit10 < 2 then state <= s5; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s6; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); if (car = '0') then state <= s6; end if; end if; end if; end if; when s6 => if Digit1 < 9 then state <= s6; Digit1 <= Digit1 + 1; if Digit10 < 0 then state <= s6; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s7; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); end if; end if; when s7 => if Digit1 < 2 then state <= s7; Digit1 <= Digit1 + 1; if Digit10 < 0 then state <= s7; Digit1 <= (others=>'0'); Digit10 <= Digit10 + 1; else state <= s0; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); end if; end if; when others => state <= s0; end case; end if; end if; end if; end process main; Digit1_o <= Digit1; Digit10_o <= Digit10; sub:process(state) begin case state is when s0 => lights <= "1011011"; when s1 => lights <= "1011011"; when s2 => lights <= "1010111"; when s3 => lights <= "1001111"; when s4 => lights <= "1101101"; when s5 => lights <= "1101101"; when s6 => lights <= "1101110"; when s7 => lights <= "1001111"; when others => lights <= "1011011"; end case; end process sub; end traffic_arch;
