Forum Discussion
JWils26
New Contributor
New ContributorTiming paths from PORT_B_WRITE_ENABLE_REG to an inferred simple dual-port RAM output - why does this path exist?
Targeting a Cyclone V SoC device, I have a lot of inferred RAM in my design. Most of them are simple single clock dual-port RAM. In the Timing Analysis there are paths from a PORT_B_WRITE_ENABLE_REG ...
JWils26New Contributor
New ContributorAlso, how do you define the read during write behaviour on the same port? The sythesis ramstyle attribute only seems to affect the mixed port relationship.
