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JWils26's avatar
JWils26
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7 years ago

Timing paths from PORT_B_WRITE_ENABLE_REG to an inferred simple dual-port RAM output - why does this path exist?

Targeting a Cyclone V SoC device, I have a lot of inferred RAM in my design. Most of them are simple single clock dual-port RAM. In the Timing Analysis there are paths from a PORT_B_WRITE_ENABLE_REG ...
GuaBin_N_Intel's avatar
GuaBin_N_Intel
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7 years ago

@JWils26​ You may be correct that it is tied to low since it is unused

  • JWils26's avatar
    JWils26
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    7 years ago

    So I guess I can cut those paths? It may help with timing throughout the design. I am concerned that when you try to locate the path in the Technology Map Viewer, it highlights the data output path, which obviously I don't want to cut!