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JWils26
New Contributor
New ContributorTiming paths from PORT_B_WRITE_ENABLE_REG to an inferred simple dual-port RAM output - why does this path exist?
Targeting a Cyclone V SoC device, I have a lot of inferred RAM in my design. Most of them are simple single clock dual-port RAM. In the Timing Analysis there are paths from a PORT_B_WRITE_ENABLE_REG ...
GuaBin_N_Intel
Contributor
ContributorI think it is because of setting of new data for read-during-write in the same port. It could not be changed anyhow. Try to register at output port where it would help the timing. Also, CV M10K performance spec can be referred to this datasheet https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf, Table 33, pg44.
JWils26New Contributor
New ContributorThat would make sense because of the naming, however it is a simple dual-port RAM, so there is no "new data" on port B, and I would assume that the write enable on port B would be tied low?
