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JWils26
New Contributor
New ContributorTiming paths from PORT_B_WRITE_ENABLE_REG to an inferred simple dual-port RAM output - why does this path exist?
Targeting a Cyclone V SoC device, I have a lot of inferred RAM in my design. Most of them are simple single clock dual-port RAM. In the Timing Analysis there are paths from a PORT_B_WRITE_ENABLE_REG ...
GuaBin_N_Intel
Contributor
ContributorBefore commenting any, can share the RAM implementation details in Fitter report > Resource Section > RAM Summary?
JWils26New Contributor
New ContributorPlease find attached an example RAM summary, one of which there exists this path.
