Occasional Contributor
Occasional ContributorHello,
Sorry for the delayed reply. I was trying to create relevant test vector inputs but was unsuccessful.
To explain the issue: The screenshot of the schematic in earlier post belongs to a file in 3rd level of instantiation. Some of the inputs to this block are generated from other blocks. Thats the reason its difficult to regenerate the behaviour without the complete project and complete set of input test vectors.
The test vectors (as mentioned earlier) are given to top level input pins.
Do you know any other way to continue solving the issue?
I can understand its difficult to answer without having the schematic and test vectors, but I would like to know if I can perform any tests as per your suggestion and post the results here.
Occasional ContributorI would like to explain the flow here: Kindly refer the schematic and simulation results side by side. I have attached the simulation screenshot for better resolution. Also, the signals in simulation result are arranged in order of the data flow for easier understanding.
Starting from OR gate OR62 -> Signal levels are proper and no unknowns ('X') in sim results.
Output of OR62 given to PRN of DFF44. As D input of DFF44 is the feedback from its own output, it is understood that during the beginning of simulation, d and q of DFF44 is X.
'q' of DFF44 is directly connected to 'd' of DFFE106. The question is: at point A in simulation screenshot (marked in white colour), why doesn't the 'd' input of DFFE106 change when 'q' output of DFF44 changes to '0'?
Even after the enable signal of DFE106 is active at point B (marked in white), the change cannot be seen. Am I missing something here?
Hope the explanation is clear.
