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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Timing issues on DFF feedback loop.

Hello, I wanted to know if the output of DFF in the attached design leads to any timing problems. What happens to DFF output if both Preset and Clear are active at the same time? CLK is 32 MHz....
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Could you provide a simple test case and testbench to reproduce the behavior?


Thanks

Best regards,

KhaiY


NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hello,

Its a large design and the test vectors are applied on top level IOs. I present the portion of schematic where I have narrowed down and found the error to be originating.

The point of interest is DFF44. Whose output is X (unknown) right from the beginning of the simulation.

CONTCLK_IN: Is the input to DFF44 and sync block.

QCLK_IN: Is the input to DFF106 

Sync block is just 2 DFF synchroniser. Circuit below:

Please have a look at the simulation output. The 'X' (unknown) has propagated to sync block and later the output of OR60 block is also X. I have attached the simulation outpt for better resolution. CTEST, CLEARN and Clock inputs are all in the simulation window.

Thank you!