Forum Discussion
Altera_Forum
Honored Contributor
14 years agoTiming errors after rerunning the design
I have added timing constraints to my design and the time quest analyzer reported no timing errors I made a very small changes in rtl file(added a register) and no change in the settings opti...
Altera_Forum
Honored Contributor
14 years agoThere can be many cases. I cant comment as your info is very less.
Were you closing timings with a small +ve slack before you added the register? Did you flopped a singlel bit signal or a bus? Generally when we register a bus then we tend to increase the register count and then the routing congestion which can lead to setup failure at times (but depends). If you were just closing timings before i.e. with a very small positive slack then it can fail timings as the place and route changes but i hope the WNS should not be much.