Timing Error

Hello,

I have a Total Negative Slack of 1646 [reduced from 17000 after adding pipeline stages in Qsys]. I have reached maximum pipeline and cannot go any further.

The Latch clock and the Launch clocks are the same. How do I solve this problem without using "set_false_path" [This basically does tells TQA not to analyse that particular path and does not solve the problem right?]

I can get rid of this error by adding "set_multicyle_path" and relaxing the timing, but is this the right way?

And also I don't get a right estimate of the Fmax unless I use the right timing exceptions right?

Addition to Above Post:

I have found that the failing path is between within the Nios and there is a huge combinational logic between the input and output.

Thanks,

Aditya