Timing Error with RGMII CycloneV SoC

Hi. I'm "720_com" of Altera beginner.

I want to solve the timing violation message.

Design : Cyclone V RGMII Example Design

http://rocketboards.org/foswiki/view/projects/cyclonevrgmiiexampledesign

I found same topics. But, there is no writing it.

http://www.alteraforum.com/forum/showthread.php?t=50845

So, I'm in trouble.

<Timing violation path>

Setup Timing violation path : TX_CLK_OUT_125

I am trying the below( 9 paths);

http://www.alteraforum.com/forum/showthread.php?t=46960

It is look like timing violation.

I want solve timing error. Please tell me about solve it.

If anyone has any idea, please tell me.

Thanks in advance.