Honored Contributor
Honored ContributorI ran a ModelSim-Altera simulation to confirm that my output (of my computation logic) is correct.
As you advised in another post, I added latency where ever necessary to try to minimize the path constraints. The problem now is that after adding some latency, and by trying to avoid using the Multicycle-approach, I keep on getting slacks at some path or the other. The weird part (at least to me) is that Quartus initially showed a slack in a path near the middle of the computational logic. Upon adding some latency/registers to correct for time delay near the middle path, Quartus then showed a slack near the starting of the design. And again upon correcting this slack using latency, a slack showed up some where in between the computation logic. Why would Quartus not start showing the slack from the top and proceed towards the end?
