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If you don't have I/O timing constraints, how do you know the ASRAM only runs at 50MHz? Or do you just put it into the system, change the clock rate, and see where it fails?
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To be honest, yes. And I haven't had such problems in the past. The only method I used to affect timing behavior was the "fast output register" logic option.
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So, how do you do the constraints? Are you using TimeQuest or the Classic Timing Analyzer?
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I use the Classic Timing Analyzer. Thanks for your detailed explanation! Sticking to what you've said, I have entered Tco and Th constraints for all my output pins (CS, BE, WE, OE, Address) as well as Tco, Th and Tsu constraints for the bidirectional (Data) pins.
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Do you register your inputs and outpouts?
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Because I need to have only two clock periods for each ASRAM access, some are, some not.
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Do you know how to check if I/O registers are being used?
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Is there another way than looking at the HDL code if there is some combinatorial logic between the last register and the pin?
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Are you using a PLL?
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Yes.
After having entered the constraints mentioned above, I still have problems with the RAM when using a system clock of 50MHz. Strange enough, it seems to work at 70MHz. I guess there might be a bus conflict on the Data signals of the 50MHz design - maybe the FPGA doesn't deassert its pins fast enough after a write access. Are the Tco and Th constraints used to affect the timing of the tri-state buffer of the pin, too?
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