Timing contraints/assignments for async. static RAM

If you don't have I/O timing constraints, how do you know the ASRAM only runs at 50MHz? Or do you just put it into the system, change the clock rate, and see where it fails? In general, Cyclone II should be running faster than Cyclone I(and Cyclone III should be even faster).

So, how do you do the constraints? Are you using TimeQuest or the Classic Timing Analyzer? For a simplistic approach, you want the fastest clock to out, and the fastest setup time, and then need to calculate how this fits into your total clock period. For example, if your data/address/control signals Tco is 7ns, your board delay is 1ns, the ASRAM Tco delay is 9ns, and your Tsu is 2ns, then you have a full round-trip delay of:

7ns(get off chip) + 1ns(board delay to ASRAM) + 9ns(through ASRAM) + 1ns(board delay back) + 2ns(clock data back onto chip) = 20ns, i.e. you could handle a 50MHz clock. Reducing the Tco and Tsu requirements would then give you better times.

Anyway, what timing engine are you using? Do you register your inputs and outpouts? Do you know how to enter IO constraints? Do you know how to check if I/O registers are being used? Are you using a PLL? These are all separate topics for constraining this, so please provide more information and hopefully we can point you in the right direction.