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I know using latch is not good design and do not want to use. Unfortunately, I must use it for my application. I need to find out how I can constraint these latch. I was thinking of using set_max_delay, but I'm not sure whether this would do it since set_max_delay is used for combinatorial logic path.
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Kattice,
Yes, Latch IS a small combinational loop by itself.
just interesting, why you cannot use the flip-flop with Synchronous Clear, because, anyway, you latch by implication depends on the Clock - it clears after 5 clock cycles.
And for me it is looks strange to provide constraints for one specific module; what if you design contains 1000 logic gates, you cannot constraint each.
Honored Contributor
