Timing constraints on between FPGA and external PLL

Hi Sstrell,

Thanks for your replying. I'd like to provide more details for your reference.

4) false path the clock output path so it's not analyzed as a data path (set_false_path)

...How does this external device's PLL work? Can you just feed a 40 MHz clock through it without any changes?

-- This DSP PLL is embedded in the DSP which can generate a local clock by multiplying the input reference clock. The original intention I used this PLL to generate 40Mhz from 20Mhz is to reduce the PCB layout timing restriction. Since 40Mhz would be easier for FPGA timing constraints as you suggested, I would try to use the 40Mhz clock between DSP and FPGA instead.

6(?) Not sure if that "interface ctrl" is outputting from the FPGA but if it is you'd need set_output_delay -max and -min as well

-- Sorry that I haven't made it clear. The depicted Databus between Interface module in DSP and Interface ctrl module in FPGA includes a 16bit data bus and some other control signals to each direction, like R/W, cs, and ready, so I reckon the set_output_delay max/min constraints are also needed.