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Actually this is how I am doing it :). Now I know that a 50 MHz SPI clock is almost equivalent to 7 clock cycles of the fast 333.33 MHz clock. I detect the negative edge on SPI and prepare my data in 3 clock cycles of the fast clock. Now if I set a multi-cycle path of 3 (virtual) clock cycles (and assuming the falling edge of SPI clock and rising edge of virtual clock are aligned), and suppose that the 3 (virtual) clock cycles are being consumed in the FPGA to prepare the data for the host, is my supposition correct and will it give me correct timing analysis?
In other words, keep my constraints as i listed them earlier and just add a 3 cycle multi-cycle path on the failing paths?
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IMHO you have to achieve valid setup and hold times to the external master by design. The 50 MHz of the SPI and the internal 333.33 MHz are to be considered as totally unrelated so you cannot express any relationship between the two. So a multi-cycle path will not bring anything. The only constraints left are the ones you originally put in, but instead of virtual_clk_sys you have to use the PLL-generated clock. A 0.0 ns max output delay gives a t(COmax) of 3.0 ns which is hard to achieve. To my idea it is better to set a false path for the spi_miso pin.
set_false-path -to }]
and to verify actual behaviour (and the obtained timings) by simulating the design.
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