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Note:
If your 50MHz signal does not directly launch output data but the fast clock does after reading the falling edge then I am afraid this further complicates timing and validity of reports.
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Actually this is how I am doing it :). Now I know that a 50 MHz SPI clock is almost equivalent to 7 clock cycles of the fast 333.33 MHz clock. I detect the negative edge on SPI and prepare my data in 3 clock cycles of the fast clock. Now if I set a multi-cycle path of 3 (virtual) clock cycles (and assuming the falling edge of SPI clock and rising edge of virtual clock are aligned), and suppose that the 3 (virtual) clock cycles are being consumed in the FPGA to prepare the data for the host, is my supposition correct and will it give me correct timing analysis?
In other words, keep my constraints as i listed them earlier and just add a 3 cycle multi-cycle path on the failing paths?
Thanks to all gurus for your help.
Honored Contributor
