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the SPI clock (50 M) is also an input to my FPGA, not its output. Also, since it is very slow compared to my system clock of 333.33 M, I just treat as a regular signal in my design and sample it with my system clock. So I did not declare it as a clock in .sdc file. Should I?
I detect falling edges on the spi clock and have to prepare data such that it is ready to be sampled by the host on the positive edges of spi clock.
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The 50 MHz incoming SPI clock must be regarded as unrelated to the 333 MHz internal clock, two clocks of 20 ns and 3 ns will at some point provoke a metastable operation.
So you need to synchronize this input wit a 2-stage synchronization chain, this takes at most 2 system clocks or 6 ns. The third clock would output the data onto the MiSo pin, bringing it to 9 nsec. Then you have to add the t(CO) of the Miso Pin, making it more then 10 ns, so it wouldn't work. If however you can use the rising edge of the incoming SPI clock to trigger the operation it it will work fine and you can write set_false_path for the MiSo pin as you will meet timing 'by design'. Setting the 'Fast Output Register' for the MiSo pin will keep the t(CO) low and you can achieve about 8ns t(SU).
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