timing constraints for SPI (or UART)

Firstly it is not clear if the 50MHz is clock input and used to launch registers or is it just data sampled by fast clock) . If it launches then it is a clock and you must declare it since it is a base clock.

Secondly, if the 50MHz is your launching SPI output data clock then the output delays should be referenced to it.

Frankly I am not sure here how delay values of timequest relate to its clock since Altera examples and doc. stress on clock and data going together in same direction. In other words, your IF is not classical source synchronous for outputs. Your latch edge in host device may even occur before its launch edge in FPGA. Moreover, an equal board trace of clock/data does not mean zero effect on timing window here.

Don't worry, to avoid maths, you can do some small research work here:

apply various delay values and check:

1) tCO and tCO min (relative to falling edge, see report datasheet)

2) tSU/tH and timing slack at io(see report io timing).

The difficult bit is how to interpret output results:

example: Assuming +1ns tSU and +.5ns tH (timing window around edge) then optimum reported should be around tSU = 9 ns and tH = - 7.5ns (timing window moved to centre of clock period).

Note:

If your 50MHz signal does not directly launch output data but the fast clock does after reading the falling edge then I am afraid this further complicates timing and validity of reports.