timing constraints for SPI (or UART)

There are several misperceptions in your approach.

declaring 100MHz ref clock is ok. deriving PLL clocks is ok.

declaring that virtual clock is a mystery to me (virtual clock is used to model an input device launch clock).

you should instead declare your output data clock (50MHz).

next you set the output delay values referred to output clock.

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...FPGA centric or system centric, both will work.

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This is an error I noted several times on this form. fpga centric can't be correct for system centric except in one case: external device does not have tSU/tH timing requirements e.g. automatic tracking...

You need system approach so that fpga knows the host tSU/tH and board delays.

If your 50MHz clock was same edge launch/latch then it becomes a standard source synchronous IF and I advise you to go that way and redesign. Alternatively, one approach is to recalculate tSU/tH... a second approach to assume a DDR like IF then cut off paths of same edge launch/latch and rise-fall launch/latch. In this case your delay values will be:

max = +tSU

min = -tH