Honored Contributor
Honored ContributorHi Rysc,
Thanks for your further insights ! Currently i have the design constrained and passing timing....using the following constraints. So at the momemt i am using the set_min_delay / set_max_delay on all output signals to the DSP from the FPGA. I have a multicycle constraint on all of the input signals from the DSP to the FPGA, using the set_input_delay -min / max style. I am not 100% sure these constraints model my physical design however. The set_max_delay is saying : as long as you get out of the FPGA in less than a clock, then we are all happy. This is the external setup to the DSP. The min delay is set to 0 for the DSP hold constraint. Is this right ? I think this may be unrealistic, and the max output delay should really be ; clock period - [DSP setup + board delays].... Maybe it would be better then if i use your other suggestion to use set_output_delay: - then for the HAS_STROBE apply this as a -clock_fall to the ADDRESS / Control signals {had[0], had[1], rdnw} - for the HAD_STROBE {rising edge clocked) apply the set_output_delay to the had[15:0] data bus signals. Question: now i have a pair of constraints applied to the had[0] had[1] signals....will TimeQuest analyze i assume both paths and report these two signals setup/hold paths for both strobes ? Many thanks :) # *************************************************************************************************************# Set Multicycles on DSP to EHPI data output bus : 2 clocks# ************************************************************************************************************* set_multicycle_path -from [get_ports {had [*]}] -to [get_registers {bidir_interface:uut|hdata [*]}] -setup -end 2 set_multicycle_path -from [get_ports {had [*]}] -to [get_registers {bidir_interface:uut|hdata [*]}] -hold -end 1 # *************************************************************************************************************# Constrain EHPI to DSP CTRL strobed output paths# *************************************************************************************************************# Output MAX delay on HAS bus : using EHPI Virtual Address strobe# set_output_delay -clock HAS_STROBE -max $HASOutputDelayMax [get_ports {had[0] had[1] hrnw}] set_max_delay -to [get_ports {had[0] had[1] hrnw}] $HASOutputDelayMax # Output MIN delay on HAD bus : using EHPI Virtual Address strobe# set_output_delay -clock HAS_STROBE -min $HASOutputDelayMin [get_ports {had[0] had[1] hrnw}] set_min_delay -to [get_ports {had[0] had[1] hrnw}] $HASOutputDelayMin # *************************************************************************************************************# Constrain DSP to EHPI Input ports# *************************************************************************************************************# input MAX delay on HAD bus : using EHPI Virtual Data Strobe set_input_delay -clock EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0]} -max $InputDelayMax [get_ports {had [*]}]# set_max_delay -from [get_ports {had [*]}] $InputDelayMax# input MIN delay on HAD bus : using EHPI Virtual Data Strobe set_input_delay -clock EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] -min $InputDelayMin [get_ports {had [*]}]# set_min_delay -from [get_ports {had [*]}] $InputDelayMin # *************************************************************************************************************# Constrain DSP to EHPI Output ports# *************************************************************************************************************# Output MAX delay on HAD bus : using EHPI Virtual clock # set_output_delay -clock HAD_STROBE -max $OutputDelayMax [get_ports {had [*]}] set_max_delay -to [get_ports {had[2] had[3] had[4] had[5] had[6] had[7] had[8] had[9] had[10] had[11] had[12] had[13] had[14] had[15]}] $HADOutputDelayMax# Output MIN delay on HAD bus : using EHPI Virtual clock # set_output_delay -clock HAD_STROBE -min $OutputDelayMin [get_ports {had [*]}] set_min_delay -to [get_ports {had[2] had[3] had[4] had[5] had[6] had[7] had[8] had[9] had[10] had[11] had[12] had[13] had[14] had[15]}] $HADOutputDelayMin
