timing constraints for EHPI DSP to FPGA asynchronous interface

Hi Rysc:

Does this sdc file look reasobale to you ? I am now using set_max_delay and set_min_delay and the HAS_STROBE is falling edge triggered ...i have

set the HASOutputDelayMax to the clock periof (12.6 ns) for setup and

the HASOutputDelayMin to 0 for hold.

On the data path, HADOutputDelayMax is also set to 12.6ns and

HADOutputDelayMin:) is set to 0 for hold.

cheers :)

# **********************************************************************************# Golden Constraints file for EHPI to DSP interface# **********************************************************************************# **********************************************************************************# Define all bas clock periods# **********************************************************************************# # Set period for EHPI base clock#

set ehpi_base_period 25.201# set virtual DSP clock used to sample EHPI generated ctrl, strobes and data

set dsp_clk_period [expr $ehpi_base_period/2]# DEFINE Timing constraints from TI Datasheet

set DSP_Th 4

set DSP_TcoMax 16# set max and min est DSP to FPGA delays

set Max_fpga2dsp 2

set Min_fpga2dsp 1# set max output delay for signals sampled by DSP from has_n strobe

set HASOutputDelayMax $dsp_clk_period# set min Output delay for signals sampled by DSP from has_n strobe

set HASOutputDelayMin 0# set max output delay for signals sampled by DSP from hds_n strobe

set HADOutputDelayMax $dsp_clk_period# set min Output delay for signals sampled by DSP from has_n strobe

set HADOutputDelayMin 0# set max INPUT delays for DSP to FPGA transfers based on EHPI MASTER CLOCK

set InputDelayMax [expr $dsp_clk_period/2] # [expr $DSP_TcoMax + $Max_fpga2dsp]# set max INPUT delays for DSP to FPGA transfers based on EHPI MASTER CLOCK

set InputDelayMin 0# [expr -1*$DSP_Th + $Min_fpga2dsp]# create constraint for input clock pin to PLL

create_clock -name inclk0 -period $ehpi_base_period [get_ports inclk0]

derive_pll_clocks

derive_clock_uncertainty# Create Generated Clock for STROBE write output HAS

create_generated_clock -invert -name HAS_STROBE -source [get_pins {EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_registers {bidir_interface:uut|has_n}]# Create Generated Clock for STROBE to output pin

create_generated_clock -name HAD_STROBE -source [get_registers {bidir_interface:uut|hds_ni}] [get_ports hds_n]

set_clock_groups -asynchronous

-group {inclk0

EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0]

HAS_STROBE

HAD_STROBE

}

# *************************************************************************************************************# Constrain EHPI to DSP CTRL strobed output paths# *************************************************************************************************************# Output MAX delay on HAS bus : using EHPI Virtual Address strobe# set_output_delay -clock HAS_STROBE -max $HASOutputDelayMax [get_ports {had[0] had[1] hrnw}]

set_max_delay -to [get_ports {had[0] had[1] hrnw}] $HASOutputDelayMax # Output MIN delay on HAD bus : using EHPI Virtual Address strobe# set_output_delay -clock HAS_STROBE -min $HASOutputDelayMin [get_ports {had[0] had[1] hrnw}]

set_min_delay -to [get_ports {had[0] had[1] hrnw}] $HASOutputDelayMin# *************************************************************************************************************# Constrain DSP to EHPI Input ports# *************************************************************************************************************# input MAX delay on HAD bus : using EHPI Virtual Data Strobe # set_input_delay -clock HAD_STROBE -max $InputDelayMax [get_ports {had

[*]}]

set_max_delay -from [get_ports {had

[*]}] $InputDelayMax# input MIN delay on HAD bus : using EHPI Virtual Data Strobe # set_input_delay -clock HAD_STROBE -min $InputDelayMin [get_ports {had

[*]}]

set_min_delay -from [get_ports {had

[*]}] $InputDelayMin# *************************************************************************************************************# Constrain DSP to EHPI Output ports# *************************************************************************************************************# Output MAX delay on HAD bus : using EHPI Virtual clock # set_output_delay -clock HAD_STROBE -max $OutputDelayMax [get_ports {had

[*]}]

set_max_delay -to [get_ports {had[2] had[3] had[4] had[5] had[6] had[7] had[8] had[9] had[10] had[11] had[12] had[13] had[14] had[15]}] $HADOutputDelayMax# Output MIN delay on HAD bus : using EHPI Virtual clock # set_output_delay -clock HAD_STROBE -min $OutputDelayMin [get_ports {had

[*]}]

set_min_delay -to [get_ports {had[2] had[3] had[4] had[5] had[6] had[7] had[8] had[9] had[10] had[11] had[12] had[13] had[14] had[15]}] $HADOutputDelayMin