timing constraints for EHPI DSP to FPGA asynchronous interface

Hi there Rysc,,,,,brilliant answer ! I have been thinking along similar lines....ie using set min and max delays on each output....but was put off

a bit by your User guide....which goes into quite some detail about the problems that these constraints can cause. But now you have confirmed its probably ok to use them in this case, i will try them.

The clock inversion is a good tip....the has_n strobe is used to strobe in the HAD bus (used as address and control bus in conjunction with has_n). The hds_n strobe is +ve edge triggered and clock in the data from the same HAD bus.

Here is my current HAS_N strobe clock def:

create_generated_clock -name HAS_STROBE -source [get_pins {EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_registers {bidir_interface:uut|has_n}]

How do i invert this ?

many thanks :)