timing constraints for EHPI DSP to FPGA asynchronous interface

Ugh. You've got a tough one. Let's step back for a second and look at what's occuring. When hcs_n is asserted, it probably has a min/max range that it needs to get out of the FPGA without causing a failure. For example, if hcs_n's delay is a cycle longer than has_n, then even though it is asserted a cycle before, it would go active after has_n.

For all of the signals above, you might be better off with a "range" rather than using standard synchronous trasfers. For example, you could constrain them all with set_max_delay 12.5 and set_min_delay 0, which is very much like a Tco range of 0ns to 12.5ns. (The User Guide talks about some of the issues with using set_max/min_delay for I/O constraints, but I think it works for you here). The nice thing is that you can tweak the values, i.e. you could make it set_max_delay 14.5 and set_min_delay 2, which shifts everything over by 2ns. Basically you're constraining everything to occur within one period, but you don't care where that period is, because your logic sends them all out on different edges and hence "sequences them".

I think you still then want to use has_n and hds_n as clocks for the address/control/data. Since they're latching on the falling edge, you might need to add -invert to the generated clock on these output ports, so the setup relationship will be shifted a half-cycle.