timing constraints for EHPI DSP to FPGA asynchronous interface

Hi Rysc,

It was buried.....when i did a node search and changed the constraint to this:

# Create Generated Clock for STROBE from PLL driving REG

create_generated_clock -name HAD_STROBE_REG -source EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] [get_registers {bidir_interface:uut|hds_ni}]

....it now works....and i beleive i now have some working (at least syntactically !) constaints. If i run the report IO timing i get lots of failling paths ...well at least thats better than none before ...so progress ..:)

Many many thanks for your help !