timing constraints for EHPI DSP to FPGA asynchronous interface

Hi Rysc, Thanks again for your brilliant help :)

I see what you mean about my generated clock error ( although i

didnt quite get what you meant about a space in the name ?)...i see i have missed off the get_registers / get_ports commands).

In the design the REG hds_ni is driven from the PLL clock output :

EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0]

The output pin is : hds_n, which is fed by the REG output. hds_ni ...so

now i have created the following constaints :

# Create Generated Clock for STROBE from PLL driving REG

create_generated_clock -name HAD_STROBE_REG -source EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] [get_registers hds_ni]# Create Generated Clock for STROBE to output pin

create_generated_clock -name HAD_STROBE -source HAD_STROBE_REG [get_ports hds_n]

Does this look remotley correct ?

When i run your report commands though i still get zero setup and hold paths for these paths.

many thanks