Honored Contributor
Honored ContributorHi Rysc, thanks for your second response, which i have been trying to implement...here s my SDC file so far, copied below. The HAS_STROBE and HAD_STROBE are both defined as clocks, HAS is the address strobe and clocks out HAD pins 0 and 1, a 2 bit address reg select to the DSP. HAD strobe clocks out the 16 bit data bus.
When i compile my design and then run 'report all I/O timings' i get the follwoing messagese for TimeQutes: Info: Report Timing: No setup paths were found Info: Report Timing: No hold paths were found Info: Report Timing: No recovery paths were found Info: Report Timing: No removal paths were found Info: Report Timing: No setup paths were found Info: Report Timing: No hold paths were found Info: Report Timing: No setup paths were found Info: Report Timing: No hold paths were found ...i wonder what i am doing wrong ! It seems just about everything so far ! thanks for your help:oops: # Define TMS320TLV5510 Timing Parameters set DSP_Tsu 4 set DSP_Th 4 set DSP_TcoMax 16 set DSP_TcoMin 6# set max and min est DSP to FPGA delays set Max_fpga2dsp 2 set Min_fpga2dsp 1# set max / min OUTPUT delays set OutputDelayMax [expr $DSP_Tsu + $Max_fpga2dsp] set OutputDelayMin [expr $DSP_TcoMin + $Min_fpga2dsp]# set max / min INPUT delays set InputDelayMax [expr $DSP_TcoMax + $Max_fpga2dsp] set InputDelayMin [expr -1*$DSP_Th + $Min_fpga2dsp]# Set period for EHPI base clock set ehpi_base_period 12.82# create constraint for input clock pin to PLL create_clock -name inclk0 -period $ehpi_base_period [get_ports inclk0] derive_pll_clocks derive_clock_uncertainty set_clock_groups -asynchronous -group {inclk0 EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] }# Create Generated Clock for STROBE write output HAS create_generated_clock -name HAS_STROBE -source EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0]# Create Generated Clock for STROBE write output HAD create_generated_clock -name HAD_STROBE -source EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] set_multicycle_path -setup 0 -to [get_clocks HAS_STROBE] set_multicycle_path -setup 0 -to [get_clocks HAD_STROBE]# *************************************************************************************************************# Set Multicycles on EHPI to DSP data output bus : 2 clocks# ************************************************************************************************************* set_multicycle_path -from [get_ports {had [*]}] -to [get_registers {bidir_interface:uut|hdata [*]}] -setup -end 2 set_multicycle_path -from [get_ports {had [*]}] -to [get_registers {bidir_interface:uut|hdata [*]}] -hold -end 1# *************************************************************************************************************# Set Multicycles on DSP to EHPI data input bus : 2 clocks# ************************************************************************************************************* set_multicycle_path -from [get_registers {bidir_interface:uut|hdout [*]}] -to [get_ports {had [*]}] -setup -start 2 set_multicycle_path -from [get_registers {bidir_interface:uut|hdout [*]}] -to [get_ports {had [*]}] -hold -start 1 # *************************************************************************************************************# Constrain DSP to EHPI Input ports# *************************************************************************************************************# input MAX delay on HAD bus : using EHPI Virtual Data Strobe set_input_delay -clock { HAD_STROBE } -max $InputDelayMax [get_ports {had [*]}]# input MIN delay on HAD bus : using EHPI Virtual Data Strobe set_input_delay -clock { HAD_STROBE } -min $InputDelayMin [get_ports {had [*]}]# input MAX delay on HAS bus : using EHPI Virtual Address strobe set_input_delay -clock { HAS_STROBE } -max $InputDelayMax [get_ports {had[0] had[1]}]# input MIN delay on HAD bus : using EHPI Virtual Address strobe set_input_delay -clock { HAS_STROBE } -min $InputDelayMin [get_ports {had[0] had[1]}]# input MAX delay on RDY, D2H ACK and D2H REQ lines : using EHPI Data Strobe set_input_delay -clock { HAD_STROBE } -max $InputDelayMax [get_ports {h2dack_n[0] h2dack_n[1] d2hreq[0] d2hreq[1] hrdy[0] hrdy[1]}]# input MAX delay on RDY, D2H ACK and D2H REQ lines : using EHPI Data Strobe set_input_delay -clock { HAD_STROBE } -min $InputDelayMin [get_ports {h2dack_n[0] h2dack_n[1] d2hreq[0] d2hreq[1] hrdy[0] hrdy[1]}]# *************************************************************************************************************# Constrain DSP to EHPI Output ports# *************************************************************************************************************# Output MAX delay on HAD bus : using EHPI Virtual clock set_output_delay -clock { HAD_STROBE } -max $OutputDelayMax [get_ports {had [*]}]# Output MIN delay on HAD bus : using EHPI Virtual clock set_output_delay -clock { HAD_STROBE } -min $OutputDelayMin [get_ports {had [*]}]# Output MAX delay on control signals hds,has,hcs : using EHPI Data Strobe set_output_delay -clock { HAD_STROBE } -max $OutputDelayMax [get_ports {has_n hcs_n[0] hcs_n[1] hds_n hrnw d2hack_n[0] d2hack_n[1]}]# Output MIN delay on control signals hds,has,hcs : using EHPI Data Strobe set_output_delay -clock { HAD_STROBE } -min $OutputDelayMin [get_ports {has_n hcs_n[0] hcs_n[1] hds_n hrnw d2hack_n[0] d2hack_n[1]}]# Output MAX delay on HAS bus : using EHPI Virtual Address strobe set_output_delay -clock { HAS_STROBE } -max $OutputDelayMax [get_ports {had[0] had[1]}]# Output MIN delay on HAD bus : using EHPI Virtual Address strobe set_output_delay -clock { HAS_STROBE } -min $OutputDelayMin [get_ports {had[0] had[1]}]
