Honored Contributor
Honored ContributorHello there and thanks for the reply. I think your analys is spot on. There are two strobes: HAS and HDS. The falling edge of HAS is intended to latch in the HAD (16 bit Multiplexed data bus) on its falling edge. The HDS strobe is intended to latch in the HAD bus (data this time) on its rising edge. There are setup and hold timings given in the TI datasheet for everything, HAS to HDS setup/hold, HAS to HAD setup/hold, HDS to HAD setup/hold etc.
My problem is that i dont know really how to implement these constraints in TimeQuest SDC format. I believe i would need to apply : set_input_delay and set_output_delay (i have been reading your excellent UserGuide here to help: pages 14-29 so far are an aid !)....but should i create a Virtual clock for the HAS and HDS strobe outputs (output from the FPGA) and time all I/O with respcet to them ? The set_multicycle_path constaint will be needed i think, because the FPGA runs at about 80MHz, and the maximum TCO from the DSP is around 16 ns...ie > 1 clock. The actual interface inside the FPGA is driven by an FSM, which inherently adds delays (ie one clock wide minimum) to each of the drievn and read signal paths...ie it delays the HDS by a clock after the HAS signal is driven low....and sets up the HAD bus for a write a clock earlye etc. In a way its self timed and self constrained i suppose. BUT this doest help Quartus and TimeQuest, which is why i still need to apply some sensible SDC timing constraints i think. Many thanks for your help, DR Positive Logic !
