Timing constraint problem while using altera ipcore

One more thing to explain in the fir core, in the coefficient fixed architecture, the register to register delay is fixed, so it will meet the fmax that mentioned in the datasheet. But for coefficient reloading architecture, the input coefficient data will first arrive coefficient register and then the core works, so the fmax is decreased due to the extra data processing in coefficient reloading part. But in fact, the coefficient reloading process is preprocessed before the fft data process. I want to add constraint in sdc file to hide the coefficient processing, for the constraint from interface to inside register is easy to add, but for register-to-register inside core I do not know how to write constraint, that upsets me.