Timing constraint problem while using altera ipcore

Thank you for your quick reply, Daixiwen.

For both of your advice, I’ve already considered them before compiling the project. In my .sdc file, I created my input clock, set it with the correct, required frequency. But after the fitter process, it still can’t meet the timing requirements.

For your second advice, I’ve think it over too. In the fir core, one of options is pipeline level, the default option is 1, but I have already set it to the maximum value 3, so how should I do next? While in the fft core, I guess there no such option for pipeline setting since I did not find any options in the Parameterize column. Your advice remind me, maybe I could add several pipelines manually in the output port, to meet requirement? But by doing so only increase the output data timing, there is no help for the data processing inside the fft core. I will try it, but it might not be useful either……