Timing Constraint problem on set_input_delay

Ok. So if I have a flash device that has no clock, but only address, data and some control signals (OE, CS, WE etc...) how do you constrain that? I am starting to understand how to constrain an interface with a clock. You basically tie your data, address and other signals to the clock that drives say the external memory device like sdram. So it seems like from what I've read, you just make sure that all of the non-clock signals meet timing relative to the sdram clock.

I'm confused though on my example because I don't have a clock going to the flash part and the setup and hold times for data and address are all relative to control lines. So for example the setup and hold times for reading data is relative to OE control line and writing data setup and hold times for address and data are relative to WE (write enable). Depending on whether you write or read from the device determines which control lines are of interest. I'm really trying to understand the time constraints world better so I'm interested to know the proper way to constrain an interface like this where there is no real CLOCK.

From studying your other posts, handbooks and the cookbook for timequest it seems like if you have a couple signals or outputs and you want to know if they meet timing relative to ONE other signal you can make this one other signal a virtual clock. Then check the setup and hold times of the group of signals against the virtual clock which ends up comparing a group of asynchronous signals against a single signal of interest. I hope this isn't confusing, but basically I have a nios ii design that talks to a flash part and in trying to learn constraints/timing better I'm trying to constrain my design. Since there is no clock to the flash part I don't know how to model the virtual clock. Same thing with a UART. How do you constrain a uart since there is no clock, I think it would be the same idea I just need some guidance.