Timing Constraint problem on set_input_delay

Your virtual clock is almost always the same period as the clock latching the data inside the FPGA. Basically your virtual clock says when data is launched. So if your virtual clock has a period of 10, it will launch data at 0, 10, 20, etc.

(If you do a "set_input_delay -clock_fall -clock virtual_clock..." then your describing another register launching at 5,15,25, etc.)

The key it to run report_timing -setup and -hold on the inputs to see what the setup and hold relationships are and that they make sense. They are based on the relationship between your external virtual clock and the internal clock latching the data.