Timing Constraint problem on set_input_delay

No paths exist between clock target "A[0]" of clock "A0_Clk" and its clock source. Assuming zero source clock latency.

Clocks can't go through registers. You have to put a generated clock on the output register:

create_generated_clock -add -name {A0_Clk_reg} -source [get_pins {u_pll1|altpll_component|auto_generated|pll1|clk[0]}] [get_keepers {r_A[0]}]

create_generated_clock -add -name {A0_Clk} -source [get_keepers {r_A[0]}] [get_ports {A[0]}]

(DDR output registers don't have this requirement because the critical path is actually the clock going through the mux select, not the register, which is why most source-synchronous output designs don't do this).

Now, it gets more complicated because you have r_A[0] feeding back into the design, so now it's data and a clock. I can see it getting ugly quickly. I would strongly suggest using Option 2.