Timing Constraint problem on set_input_delay

This one is ugly. There are two ways to do it:

1) The really ugly one is to constrain the D inputs in relation to the A outputs. I wouldn't use reference_pin(I never use reference_pin, as I find the generated_clock can do the same thing and adds more flexibility). So you can do something like:

create_generated_clock -name A0_clk -source [get_pins {*|clk[0]}] [get_ports {A[0]}]

This pretends A[0] is a clock. Then constrain D in relation, i.e.:

set_input_delay -clock A0_clk -max $max_roundtrip_delay [get_ports {D[*]}]

set_input_delay -clock A0_clk -min $min_roundtrip_delay [get_ports {D[*]}]

Where the $oundtrip_delay values are substituted with the max and min delays from A back to the D inputs.

You could then repeat this for each address bit. Note that you'll get timing between all these clocks, so you'll want to do a set_clock_groups to separate the A clocks apart.

The benefit of this is that if the A bits change, the constraints on D will change accordingly. The downside is it's a really complex mess.

Option 2 is to constrain A to a tight window. For example, do something like:

create_clock -name virt_clk -period $period

set_output_delay -clock virt_clk -max $period [get_ports A[*]]

Where period is your clock period. This will create an external virtual clock, so the setup relationship to this will be $period. Your set_output_delay then says there is an external delay of $period already being used up. So when you compile, this will fail timing. Then loosen the set_output_delay just enough that it meets timing. That way you know your A output won't be longer than X. You can also set a min delay on it.

Now that you know the max and min window that A takes to get out, you can then feed that information around and calculate a requirement on D's input. Then go in and constrain that accordingly.

This is hard to do without numbers, so I'm not giving all the details, but hopefully it makes sense. I actually think this is easier to do then the first option.