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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Timing constrain setting for uart

I am thinking about how to set timing constrain for uart. It's actually sampled by FPGA internnal system clock. For example, if uart baudrate is set 115200 bps, I use FPGA pll clock = 50MHz is quite e...
  • ak6dn's avatar
    ak6dn
    3 years ago

    Your observations are correct. You are sampling an asynchronous signal using (I expect) a dual rank clocked synchronizer approach. So there is no timing constraint (setup/hold) applicable on the data input to that input register. It is totally asynchronous.

    I have a very similar UART module in a design I have that samples the RX input at 50MHz. In the .sdc file I have:

    set_false_path -to [get_ports {UART_*}]

    and no other timing constraints on the UART_* inputs.

ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
3 years ago

Your observations are correct. You are sampling an asynchronous signal using (I expect) a dual rank clocked synchronizer approach. So there is no timing constraint (setup/hold) applicable on the data input to that input register. It is totally asynchronous.

I have a very similar UART module in a design I have that samples the RX input at 50MHz. In the .sdc file I have:

set_false_path -to [get_ports {UART_*}]

and no other timing constraints on the UART_* inputs.