mappy5
New Contributor
New Contributortiming analyzer relationship
What is the reason why Relationship becomes half clock in timing analysis?
Forum Discussion
mappy5New Contributor
New ContributorIt cannot be started by the FF of the inverting clock.
There is some unnecessary logic for the clock path.
Is Relationship sometimes not set correctly if there is unnecessary logic for the clock path?
Michael19New Contributor
New ContributorAny logic in the clock path will add some delay to the clocks latency values, even if it is not inverting it.
And if this logic perchance inverts the clock, i would assume that this adds half a clock period in addition.
If it is unneccessary logic, get rid of it.
Else try at least to analyze this logic. Can't you produce a timing report which shows your clock-paths in detail?
Try to see how the tool is implementing this in the fpga's fabric. If it for some reason can't use the specialized clock routing ressources to connect to your FF, you get tons of unnecessary delay.
