Timing analysis error: Modelsim error vsim-3039

The timing netlist will be output from the compiler. And is probably in a different language to the test bench. Hence the problem.

Honestly - if you did good design practice and it meets your timing requirements, its probably quicker just to load the design on the chip and see if it works than run a timing simulation (11 years in the industry - ive never had to run a single timing simulation)