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Altera_Forum
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10 years ago

Timing analysis error: Modelsim error vsim-3039

I have an 8b counter for learning timing analysis. I have completed Fitter, Assember, Timequest and EDA Netlist without any error. I have added the sdc file to the Assignment. When I run the gate lev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thank you for the feedback. My code is strictly VHDL. Does it mean that I have some Verilog code there? I am attaching the code. Can you help me understand what is mixed here?