Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi,
Is your design purely combinational one or sequential (clocked)? If its combinational one, you need to specify the IO constraints, max delay, etc. If its a clocked design, you need to specify the clocks, false paths, multi-cycle paths, IO delays, etc. Running the entire flow without specifying any constraints is akin to un-constrained synthesis and PNR, and can cause issues . Make sure you specify the design constraints in the SDC file or use the tool to specify it.