TimeQuest with Stratix III to Stratix III I/F

Fanning a single clock is easiest, but forces lower clock rates. Since you're registering your inputs and outputs(and most likely I/O registers get used, which will happen automatically due to your timing constraints), the output timing of an FPGA should not be affected by the input timing, or vice-versa. My feeling is that you should be able to do this without going source-synchronous, but I don't know all the details. (I would recomend using a PLL).